Phase lock loop (i.e.--PLL) is used in a variety of integrated circuits. Prior art PLLs are comprised of a phase detector, a loop filter, a voltage controlled oscillator (i.e.--VCO) and a frequency divider (See: Phase Locked Loops, Design Simulations and Applications, Roland E. Best, 1997 Mc-Graw Hill, ISBN 0-07-006051-7, PG. 91-177). The PLL receives a reference signal REF having a frequency of Fref, from an external signal source and outputs a signal VCOS having a frequency of Fvco. The frequency divider receives an VCOS and outputs a signal FD having a frequency of (Fvco/N). Usually, N is proportional to Fvco. Prior art PLL have a transfer function Hpa(s) which have a bandwidth BWpa.
A premium is placed upon the rejection of high frequency noise and error signals. These high frequency signals can increase the frequency jitter of the PLL. A better rejection can be achieved by introducing a third pole Fpole3 to transfer function Hpa(s), wherein Fpole&gt;=BWpa.
U.S. Pat. No. 5,654,675 of Bruccoleri et al discloses a phase lock loop with a transfer function that has a third pole. This PLL includes a phase detector, a charge pump, a low pass filter and a VCO. The VCO is coupled to a Resistor Capacitor (i.e.--RC) network, for providing the third pole in the transfer gain of the PLL. The R-C network includes a variable capacitor C1, three resistors R1, R2 and R3 three transistors T1, T2, T3 and a current source I. The capacitance of C1 is controlled by a digital to analog converter (i.e.--DAC). A disadvantage of this solution is that the RC network elements produce noise, this noise is received by the VCO, and increases the frequency jitter. Another disadvantage of this solution is the production of quantization errors by the DAC, which increase the frequency jitter of the VCO.
In many PLLs the phase detector provides a digital signal, that is converted to an analog signal, wherein the analog signal is eventually used to control Fvco. Some PLLs use sigma-delta modulators in order to improve the digital to analog conversion (See: U.S. Pat. No. 5,625,358 of Wilson et al).
Sigma delta conversion use over-sampling and noise shaping techniques to force error signal resulting from the conversion outside a predetermined frequency BWsd. Usually, BWsd is dependent upon the over-sampling ratio OSR, the OSR being the ratio of the sampling frequency Fsam to the Nyquist frequency 2*Fref. Larger OSR result in larger BWsd. Ususlly, BWsd&gt;Bwpa so that these high frequency signals are rejected by the PLL.
A sigma delta is usually followed by a low pass filter, for rejecting the error signals. The rejection of the error signals is very significant in PLL that have a sigma delta modulator. Without a low pass filter these error signals can increase the frequency and phase jitter of the PLL.
The over sampling ratio OSR, and accordingly BWsd change when the frequency Ferf changes. There is a need to have a low pass filter, that introduces a pole Fpole in the transfer function of the PLL, wherein Fpole tracks BWsd.
In many prior art PLL, the VCO receives an input signal that has a limited number of possible values. The VCO provides a required frequency Fref by switching between two discrete frequencies, such that the average value yields the required frequency. This method involved providing the VCO with two discrete control signals. A disadvantage of such a method is that the switching can produce noise and increase the frequency jitter of the VCO. There is a need to have a low pass filter for averaging the discrete input signals provided to the VCO.